1. Field of Invention
The present invention relates to a double spacer structure for mixed-mode IC and its manufacturing method. More particularly, the present invention relates to a double spacer structure for mixed-mode IC and its manufacturing method that utilizes a two-step-etching process.
2. Description of Related Art
Conventional mixed-mode IC includes embedded dynamic random access memory (embedded DRAM), embedded static random access memory (embedded SRAM) and application specific integrated circuit (ASIC). In a mixed-mode IC, there are at least two types of transistor devices, for example, memory devices and logic devices. According to the design rules and their corresponding differences in gate is oxide dimensions a different operational voltage must be applied to the gate of each type of transistor device. For example, a device such as a memory device having a gate oxide layer thickness of about 50 .ANG. and a gate length of about 0.25 .mu.m, the gate operational voltage is about 2.5V; for a device such as a peripheral circuit device having a gate oxide thickness of about 70 .ANG. and a gate length of about 0.34 .mu.m, the gate operational voltage is about 3.3V; and for a device such as a high voltage device having a gate oxide thickness of about 120 .ANG. and a gate length of about 0.5 .mu.m, the gate operational voltage is about 5.0V.
In mixed-mode ICs, each transistor device has its own spacer structure whose width varies according to the design rules. The spacer is a means to provide a suitable resistance for the transistor channel. If the spacer width is too short, electric field between the source and the drain terminal of a transistor will be too strong and will lead to device reliability issues, for example, hot carrier problem or short channel problem. On the other hand, if the spacer width is too long, driving current between the source and the drain terminal will be too low. The main defect in the conventional method of spacer production is that there is no systematic process for the simultaneous production of spacers having different width to satisfy the needs of different types of transistor devices.
In light of the foregoing, there is a need in the art for improving the method of spacer formation.